In recent years, the development of portable telecommunications and laptop computers has become a major driving force in the design and technology of semiconductor IC's. This growing market requires low power, high-density and electrically re-writable nonvolatile memories. Electrically erasable programmable read only memories (EEPROM) which are electrically erased on a byte-by-byte basis is one choice. However, the cell size of this type of memory is too large for such applications, and thus flash memory is another choice because of its small size and high reliability.
For achieving a high density memory device Kazerounian et al., introduced a virtual ground concept using alternative metal virtual ground (AMG) to fabricate EPROM in the paper, by R. Kazerounian et al. titled "Alternate Metal Virtual Ground EPROM Array Implemented in a 0.8 .mu.m Process for Very High Density Applications", IEDM Tech. Dig., p. 311, 1991. The synoptic layout and cross-section of this memory array are shown in FIGS. 1a-b, The front end of the process is a standard n-well CMOS process. After LOCOS field oxidation and EPROM gate a layer of the polysilicon 10 is deposited, an ONO dielectric layer 15 is then formed on the top of polysilicon 10. The ONO 15/poly-Si 10 is then patterned in elongated strips across each segment. Subsequently, a self-aligned arsenic implant is applied to form bit lines 20. An oxidation process combined with the CMOS gate oxidation process is done to form a gate oxide and grow a bit line oxide. The process continues with doped polysilicon 25 and tungsten silicide 35 deposition. A self-aligned stack gate etch process is employed to define word line 25 and floating gate cell 40. The advantages of this array are reduction of drain turn-on induced punchthrough and the allowance of scaling of effective channel length to as low as 0.25 .mu.m.
Later, the virtual ground concept then was applied to manufacture low voltage NOR virtual ground power flash memories by Bergemontet, et al. according to their flash memory with a fast access time. Their desing is set forth in the reference by A. Bergemont, et al., "Low voltage NVGTM: A New High Performance 3 V/5 V Flash Technology for portable Computing and Telecommunications Applications", IEEE Trans. Electron Devices, ED-43, p. 1510, 1996. The architecture of NVGTM is similar to AMG EPROM and features a one metal bit-line shared between two columns of cells. These metal bit-lines are strapped to every other diffusion bit-line (stripped, continuous bit lines) through the selected transistors.